Jan Yin Chan Electronics Co.,LTD. 386SX Single Chip PC
M6117D : System on a chip
DM&P
Jan Yin Chan Electronics Co,. LTD. M6117D 386SX Single Chip PC Page 31
8F-1,No.22,Wuchyuan 2RD.,Hsin Chuang city Taipei Hsien, Taiwan, R.O.C. Tel: 886-(02) 2298-0770 Fax: (02) 2299-1883
4.5.2 System Management Interrupt (SMI)
System management interrupt has the most priority to cause M6117D entering HSM space. Like non-maskable interrupt
(NMI), M6117D will jump to SMI entry point or starting address, ROM area 0FFFFFF90h in default, after accepting SMI, this
chip thus has entered HSM space. Depending on different applications, we can also change the page address of SMI entry
point by way of updating the value of UGRS’ which is a special 32-bit register in M6117 CPU core. For instance, if we write
0A0000h to UGRS before activating SMI, then M6117 will jump to 00AFF90h when SMI asserts. Following is a short sample
of assembly code to implement the example above.
MOV EAX, 0A0000h
; LDUSR UGRS, EAX
DB 0D6h, 0CAh, 03h, 0A0h
4.5.3 Enter and Exit the HSM(Hyper State Mode) space
If we select SMI to implement Power Management Mode, the CPU will switch memory space to HSM while an event
happens. Also, we can use the instruction BRKPM(
opcode - DB 0F1h) to enter HSM. The PV monitor interrupt (set by
CR03h PMON) and opcode trap(set by CR0Eh TOP and CR0Fh TCON) can do the same operation.
The BRKPM (opcode - DB 0F1h) instruction or any equivalent interrupt transfers the values, which have been set before its
generation with the registers indispensable in controlling the processor operation, to the high-order general purpose
registers(shown below), and then switches the processor space to shift control to the specific physical addresses. Then CPU
is brought to the following reset state:
16-bit context
Real Mode Addressing
Paging Off
Interrupt Disable
SMI, BRKPM instruction EXP monitor
PV monitor, and opcode trap
GR31
CR00h
- CR0
GR31
CR00h
- CR0
GR30
EFLAGS
GR30
EFLAGS
GR29
AR1
- CS-LIMIT
GR29
AR1
- CS-LIMIT
GR28
SR1
- CS-BASE
GR28
SR1
- CS-BASE
GR27
EIP
GR27
EIP
GR26
GR26
EXT#
GR25
CS
GR25
CS
The RETPM (opcode - DB 0D6h 0E6h) instruction causes the reverse operation of the BRKPM instruction. It returns control
to the normal context. Note that save/restore is done only for
CR00h, AR1, EFLAGS, SR1, EIP, and CS for both BRKPM and
RETPM instructions. Therefore, the contents of the other registers must be saved and restored by software.
When the original operating system is in protected mode and we enter HSM space, we need to handle the segment base and
attribute registers carefully when the segment register is changed. Also, we can get other information from reading the
GR31
-
GR25 to do our application.
(45 Seiten)
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