Jan Yin Chan Electronics Co.,LTD. 386SX Single Chip PC
M6117D : System on a chip
DM&P
Jan Yin Chan Electronics Co,. LTD. M6117D 386SX Single Chip PC Page 1
8F-1,No.22,Wuchyuan 2RD.,Hsin Chuang city Taipei Hsien, Taiwan, R.O.C. Tel: 886-(02) 2298-0770 Fax: (02) 2299-1883
Section 1 : Introduction
The M6117D is a highly integrated, low voltage,
single-chip implementation of Intel
TM
386SX compatible
microprocessor plus ALi M1217B chipset. The M6117D
provides the following functions : 1) Intel
TM
386SX core
2)Supports EDO DRAM controller including FP mode 3)
Coprocessor Interface 4) ISA interface 5) Peripheral
Interface (includes two cascaded 8237 DMA controllers, a
74612 memory mapper, 2 cascaded 8259 interrupt
controller, and an 8254 programmer counter 6) Built-in
RTC 7) Programmable 2 channels chip select 8) Built-in
PS2 Keyboard Controller and Mouse 9) Built-in
WATCHDOG timer 10) 16-bits GPI/O via SD bus and
16-bits independent GPIO 11) IDE interface .
The following sections highlight the main features and
functions of the M6117D chip. For additional information,
see Section 3 of this data sheet.
1.1 Features and Functions
Static Intel 386SX compatible Core
• Operating Power Supply 5.0V
•
Operating frequency 25Mhz to 40Mhz
Memory Controller
• Supports EDO DRAM
• Supports on board memory size up to 16M bytes for
386SX or 64M bytes upgrade system using 256K,
512K, 1M, 4M or 16M SIMMs
• Supports up to 4-bank DRAM interface
• Page interleave DRAM access for FP mode
• Programmable shadow RAM from A to B segment in
128K byte and C to F segment in 32K byte unit
• Provides "RAS only" refresh or "CAS before RAS”
refresh types
• Parity generation and checking
Peripheral Interface
• Includes 2 cascaded 8237 DMA controllers
• Includes 1 74612 memory mapper
• Includes 2 cascaded 8259 interrupt controllers
• Includes 1 8254 programming counter
ISA Interface
• Executes cycles for requests from CPU, DMA and ISA
bus master
• Assembles or de-assembles data for multiple bus
cycle or unmatched data width
• Generates refresh signals to ISA slots during DRAM
refresh cycles
Built-in RTC
• Internal Real Time Clock that provides 128 byte
CMOS RAM
Programmable 2 channels chip select
• Provide chip select for memory or I/O device without
external address decode random logic
Built-In PS2/AT Keyboard Controller
• Internal PS2/AT keyboard controller and mouse
PMU interface
• Supports CPU SMM mode, SMI feature
• Supports APM control
• Provides External Suspend mode switch
• Provides four (4) system states for power saving (On,
Doze, Standby, Suspend)
• Supports RTC alarm wake up control
Expandable GPI/O signals
• Provides sixteen External power control input and
output signals
• Provides sixteen independent pin for general
purpose input and output signals
Watchdog timer
• When timer times out , a system reset or NMI or IRQ
happens
IDE interface
• Provides a decoder for external IDE connection
Packaging
• 208-pin PQFP package
(45 Seiten)
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